C-Series M.2 SSD DAS FET Burnout Root Cause Analysis and LI Process Improvement

Overview

DAS stands for Device Active Signal. In this M.2 SSD design, the controller GP21 signal drives the DAS FET, which controls the host-side LED interface. A current limiter and a 100 kOhm pull-up to 3.3V_lim are applied on the interface side.

The C-Series M.2 SSD product family entered mass production in January 2021; that date provides product background, not the investigation start date. During LI, or Label Attachment & Interface Test, intermittent DAS-related failures were observed, and FET burnout was confirmed in 35.3% of the collected DAS-fail samples analyzed.

Across the defined April 2021–March 2023 comparison period, 144 collected and confirmed FET-burnout cases among 20,696,833 units corresponded to a combined rate of 6.96 ppm, reported as approximately 7 ppm. Across the annual before-and-after windows, the rate declined from 122 cases among 11,365,245 units before the countermeasures—10.73 ppm, reported as 11 ppm—to 22 cases among 9,331,588 units afterward—2.36 ppm, reported as 2 ppm.

The trend included intermittent PPM spikes, including a March 2021 observation outside the defined comparison period. Supplier concentration, gold-finger scratch and conductive-debris evidence, PCB/socket dimensional and alignment risk, and a controlled 3.3V_EXT-to-LED short reproduction supported the occurrence analysis. Separately, DAS-related waveform measurements and retest behavior showed that the previous count-based DAS Check could miss an already affected unit. The countermeasure package therefore combined occurrence prevention with improved detection.

My direct contribution included retrieving affected units for confirmation, reproducing and retesting the failures, measuring DAS-related waveforms, modifying the DAS Check PGM, performing hardware failure analysis, measuring and analyzing PCB dimensions, consolidating cross-period and supplier trends, reviewing screening and process evidence, coordinating investigation inputs, and validating the before-and-after defect-rate change. Equipment-side and PCB-supplier source improvements were implemented through cross-functional collaboration.

Terminology

• DAS: Device Active Signal, a signal used to control the host-side LED status and check connection/activity behavior through the controller and DAS FET path.
• FET: Field-effect transistor, the switching device used in the DAS-related LED interface circuit.
• LI: Label Attachment & Interface Test, a late-stage SSD process covering label/shipment-related checks, process-mix control, unique information writing, interface validation, hardware checks, and PHY/power-management tests.
• DAS Fail / 4502: An internal LI fail condition related to DAS behavior.
• 4590: An internal recognition/contact-related fail pattern used here as a monitoring signal for socket/contact abnormality.
• Gold finger: The exposed plated edge connector contacts of the M.2 SSD.
• 3.3V_EXT: External 3.3 V supply contact on the M.2 interface.
• LED contact: The host-side LED/DAS-related interface contact.
• CPK: Process capability index used to evaluate dimensional process capability and variation against specification limits.
• AVI: Automated visual inspection.
• PGM: Test program logic used in the SSD test process.
• CTRL: Controller, the SSD controller IC.

Problem

DAS FET burnout was observed on the DAS-related circuit. Confirmed samples showed burnt marks near the DAS FET area, solder-side abnormality around the affected circuit, internal chip burnout, and DAS fail or other LI fail-code patterns before final DAS fail classification.

Only 24% of FET-burnout SSDs had 4502 DAS Fail as the prime fail code, but approximately 75% had 4502 DAS Fail as the final fail code. This shift suggested that damage could be generated or exposed during repeated LI test cycles; it did not establish identical timing for every sample.

Because SSDs can be inserted and retested multiple times during LI, repeated socket insertion and removal became a key investigation direction.

Data Boundary

• FET burnout statistics are based on SSDs collected and confirmed as FET burnout cases.
• If some SSDs were shipped out and not collected for analysis, those cases may not be included.
• All rates in this case should be interpreted as collected/confirmed FET burnout rates, not absolute field occurrence rates.
• The public case uses generalized manufacturing context and omits real customer names, equipment IDs, internal report names, raw logs, and proprietary drawings.

Data Used / Data Signals

• Collected DAS-fail samples and confirmed FET-burnout results: 35.3% confirmation among the collected DAS-fail samples analyzed
• Defined comparison period, April 2021–March 2023: 144 confirmed cases / 20,696,833 units, 6.96 ppm, reported as approximately 7 ppm
• Before window, April 2021–March 2022: 122 / 11,365,245, 10.73 ppm, reported as 11 ppm
• Post-action window, April 2022–March 2023: 22 / 9,331,588, 2.36 ppm, reported as 2 ppm
• One-sided Fisher’s exact test using the cumulative hypergeometric distribution: p < 0.001 at α = 0.05
• Two-sided 95% Clopper–Pearson exact binomial confidence intervals: 8.91–12.82 ppm before and 1.48–3.57 ppm after
• Monthly trend and intermittent PPM spikes, including 2021-03, 2021-07, 2021-09, and 2022-01
• PCB supplier concentration: PCB Supplier A 15.7 ppm vs PCB Suppliers B and C 0.7 ppm
• Prime and final fail-code sequences across repeated LI cycles: 24% prime 4502 DAS Fail vs approximately 75% final 4502 DAS Fail
• Affected-unit retrieval, retest, hardware failure analysis, and failure reproduction
• DAS-related waveform measurements during retest and screening-condition review
• Previous and revised DAS Check PGM behavior, including observed final_das_cnt outputs on the same evaluated damaged sample
• PCB dimensional measurements and CPK analysis
• Gold-finger scratch and conductive-debris observations
• Controlled 3.3V_EXT-to-LED short-path reproduction

Approach

The investigation identified a causal chain with separate occurrence and escape mechanisms. For occurrence, affected units were retrieved, confirmed, reproduced, and retested; hardware damage, gold-finger condition, conductive debris, supplier trends, PCB dimensions, socket interaction, and repeated LI cycles were reviewed together. Repeated insertion and removal increased contact-wear and mechanical-interaction risk, while PCB/socket tolerance stack-up and lateral SSD movement reduced contact margin.

Gold-finger scratch and conductive debris were observed, and conductive debris or contact overlap could create a 3.3V_EXT-to-LED short. A controlled short-path reproduction induced DAS FET burnout, supporting the physical mechanism without proving that every collected case followed the identical debris path. The 15.7 ppm rate for PCB Supplier A versus 0.7 ppm for PCB Suppliers B and C justified targeted review of contact geometry and PCB/socket tolerance stack-up; the concentration was an investigation signal, not standalone proof of a supplier material mechanism.

For escape, DAS-related waveforms were measured during retest and screening-condition review. The previous DAS Check primarily judged detected toggle count, so the evaluated damaged sample could pass when it still produced final_das_cnt = 5 without adequate evaluation of LED and GP21 voltage levels, waveform swing, VIH/VIL margin, final voltage state, leakage, or degraded FET behavior.

The Controller Test Platform A test condition and DAS Check PGM were both revised to improve detection beyond simple toggle-count observation; I directly modified the PGM. Under the combined revised condition, the same evaluated damaged sample produced final_das_cnt = 1 and was classified as Check DAS Fail. The values 5 and 1 are observed outputs for that sample, not configuration thresholds changed from 5 to 1, and the case does not isolate the separate effect of the platform-condition change from the PGM change.

Investigation Focus

• The cross-period trend showed intermittent collected/confirmed PPM spikes, including 2021-03, 2021-07, 2021-09, and 2022-01, rather than a stable process baseline.
• Only 24% of confirmed burnout samples had prime 4502 DAS Fail, while approximately 75% had final 4502 DAS Fail, directing attention to repeated LI and retest-cycle behavior.
• PCB Supplier A measured 15.7 ppm versus 0.7 ppm for PCB Suppliers B and C. This concentration justified dimensional and contact-geometry review but was not standalone proof of a supplier material mechanism.
• Gold-finger scratches and conductive debris were observed; a controlled 3.3V_EXT-to-LED short-path reproduction induced DAS FET burnout.

PCB and Socket Process Review

• Two key notch/interface dimensions were below the internal CPK target of 1.33: Dimension A, the SSD Key Notch width, had CPK 0.85; Dimension C, the center-to-center distance from the SSD Key Notch centerline to the first adjacent gold-finger contact on the shorter gold-finger side, had CPK 0.80. Individual measurements could remain within specification while capability remained below target, indicating insufficient margin and excessive variation for the PCB/socket tolerance stack-up.

Screening Logic Review

• DAS-related waveform measurements showed why the previous count-based check was insufficient: the evaluated damaged sample produced final_das_cnt = 5 and could pass without adequate review of voltage-level quality, waveform swing, VIH/VIL margin, final state, leakage, or degraded FET behavior.
• After the Controller Test Platform A test condition and DAS Check PGM were revised, the same evaluated damaged sample produced final_das_cnt = 1 and was classified as Check DAS Fail; 5 and 1 are observed outputs, not thresholds configured from one value to the other.
• Across the defined annual comparison windows, the collected/confirmed rate declined from 10.73 ppm, reported as 11 ppm, to 2.36 ppm, reported as 2 ppm; a one-sided Fisher’s exact test gave p < 0.001 at α = 0.05.

Key Investigation Choices

Root Cause / Key Finding

Occurrence mechanism: repeated LI insertion/removal increased contact-wear and mechanical-interaction risk; observed gold-finger wear and conductive debris, together with PCB/socket tolerance stack-up and lateral SSD movement, reduced contact margin. Conductive debris or contact overlap could form a 3.3V_EXT-to-LED short, and the controlled short-path reproduction induced DAS FET burnout. This supports the causal chain without asserting that every burnout case followed the identical debris mechanism.

Escape mechanism: the previous DAS Check was primarily count-based. An affected sample could pass when five toggles were still detected without adequate evaluation of LED and GP21 voltage levels, waveform swing, VIH/VIL margin, final voltage state, leakage, or degraded FET behavior. Waveform measurement and retest evidence informed the screening-condition and PGM review.

Revised detection behavior: after the Controller Test Platform A test condition and DAS Check PGM were revised, the same evaluated damaged sample produced final_das_cnt = 1 instead of final_das_cnt = 5 under the previous condition and was classified as Check DAS Fail. The values are observed sample outputs, and the combined revision does not isolate the separate effect of each change.

Corrective Actions

• AVI inspection criteria were improved to increase detection of affected samples and previously missed visual indicators.
• The Controller Test Platform A test condition and DAS Check PGM were revised to improve detection of degraded FET behavior beyond simple toggle-count observation. I directly modified the PGM; the equipment-side test-condition change was implemented through cross-functional collaboration.
• Cross-functional teams implemented and confirmed PCB Supplier A dimensional capability improvements. Separate supplier-reported characteristics, retained under the anonymized labels V and X2, improved from CPK 1.34 to 1.84 and from 1.43 to 2.37 respectively; their exact geometric definitions are not asserted, and they are not mapped to Dimensions A or C.
• The router-bit replacement interval was shortened from 2 m to 1 m of accumulated routing length to reduce tool-wear-related dimensional variation.
• The LI socket keying feature width changed from 1.10 ± 0.05 mm to 1.13 ± 0.01 mm to reduce lateral movement during insertion.
• Socket-lifetime management was strengthened to reduce socket/contact wear risk.
• 4590-rate monitoring was strengthened as a control for socket/contact abnormality.

Result & Impact

Across the defined annual comparison windows, the collected/confirmed FET-burnout rate declined from 122 cases among 11,365,245 units before the countermeasures—10.73 ppm, with a two-sided 95% Clopper–Pearson exact binomial confidence interval of 8.91–12.82 ppm—to 22 cases among 9,331,588 units afterward—2.36 ppm, with a 95% exact confidence interval of 1.48–3.57 ppm. A one-sided Fisher’s exact test using the cumulative hypergeometric distribution showed that the post-action collected/confirmed rate was significantly lower (p < 0.001, α = 0.05). The investigation connected an occurrence mechanism involving conductive debris and PCB/socket alignment risk with an escape mechanism in the previous count-based DAS Check. After the Controller Test Platform A test condition and DAS Check PGM were revised, the evaluated damaged sample produced final_das_cnt = 1 instead of 5 and was classified as Check DAS Fail. These values were observed outputs for the same sample, not configuration thresholds. The statistical result supports the observed improvement after the combined countermeasure package; it does not isolate the causal contribution of each individual action.

Methods & Tools

• Failure Analysis
• Root Cause Analysis
• Yield Improvement
• Factory Data Analysis
• Statistical Validation
• Corrective Action

Notes

• Intermittent yield spikes require trend-based investigation rather than only lot-level reaction.
• Prime and final fail-code comparison can reveal whether a defect may be generated during repeated retest cycles.
• Mechanical contact wear and conductive debris can become electrical failure mechanisms in high-volume socket insertion processes.
• A test can miss real hardware damage if it checks only digital toggle behavior without checking voltage-level quality or waveform margin.
• Strong quality improvement needs both generation-prevention actions and screening-improvement actions.
• Statistical validation can support an observed collected/confirmed rate reduction without isolating each action’s causal effect.